Datasheet

Signal Definitions
62 Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB
agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together, every other common clock.
Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are wire-OR
signals which must connect the appropriate pins of all processor FSB agents. In order to avoid
wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, HIT# and
HITM# are activated on specific clock edges and sampled on specific clock edges.
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of
IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This
transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#.
IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and
continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a noncontrol floating-point instruction if a previous floating-point
instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O
write instruction, it must be valid a 6 clks before the I/O write’s response.
INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting
their internal caches or floating-point registers. Each processor then begins execution at the
power-on Reset vector configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the
appropriate pins of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor
executes its Built-in Self-Test (BIST).
LINT0/INTR
LINT1/NMI
I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB agents. When the
APIC functionality is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are asynchronous.
These signals must be software configured via BIOS programming of the APIC register space to be
used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation
of these pins as LINT[1:0] is the default configuration.
LOCK# I/O LOCK# indicates to the system that a set of transactions must occur atomically. This signal must
connect the appropriate pins of all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait
until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the
processor FSB throughout the bus locked operation and ensure the atomicity of lock.
MCERR# I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error or a bus protocol
violation. It may be driven by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level. Assertion options are defined as
follows:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32 Intel
®
Software
Developer’s Manual, Volume 3: System Programming Guide or the BIOS Writer’s Guide which
includes the Dual-Core Intel Xeon processor 7000 series.
Since multiple agents may drive this signal at the same time, MCERR# is a wired-OR signal which
must connect the appropriate pins of all processor FSB agents. In order to avoid wire-OR glitches
associated with simultaneous edge transitions driven by multiple drivers, MCERR# is activated on
specific clock edges and sampled on specific clock edges.
Table 5-1. Signal Definitions (Sheet 4 of 7)
Name Type Description