Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 41
Datasheet Volume One, February 2014
Power Management
The memory controller transitions the DRAM to power-down by de-asserting CKE and
driving a NOP command. The memory controller will tri-state all DDR interface lands
except CKE (de-asserted) and ODT while in power-down. The memory controller will
transition the DRAM out of power-down state by synchronously asserting CKE and
driving a NOP command.
When CKE is off the internal DDR clock is disabled and the DDR power is significantly
reduced.
The DDR defines three levels of power-down:
• Active power-down: This mode is entered if there are open pages when CKE is de-
asserted. In this mode the open pages are retained. Existing this mode is 3 - 5
DCLK cycles.
• Precharge power-down fast exit: This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Existing this mode is 3 - 5 DCLK cycles.
Difference from the active power-down mode is that when waking up all page-
buffers are empty.
• Precharge power-down slow exit: In this mode the data-in DLL’s on DDR are off.
Existing this mode is 3 - 5 DCLK cycles until the first command is allowed, but
about 16 cycles until first data is allowed.
3.3.2 Self Refresh
The Power Control Unit (PCU) may request the memory controller to place the DRAMs
in self refresh state. Self refresh per channel is supported. The BIOS can put the
channel in self-refresh if software remaps memory to use a subset of all channels. Also
processor channels can enter self refresh autonomously without PCU instruction when
the package is in a package C0 state.
3.3.2.1 Self Refresh Entry
Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter
always clears with any access to the memory controller and remains clear as long as
the memory controller is not drained. As soon as the memory controller is drained, the
counter starts counting, and when it reaches the idle-count, the memory controller will
place the DRAMs in self refresh state.
Power may be removed from the memory controller core at this point. But V
VMSE
supply
(1.5 V or 1.35 V) to the DDR IO must be maintained.
3.3.2.2 Self Refresh Exit
Self refresh exit can be either a message from an external unit (PCU in most
cases, but also possibly from any message-channel master) or as reaction for an
incoming transaction.
Here are the proper actions on self refresh exit:
• CK is enabled, and four CK cycles driven.
• When proper skew between Address/Command and CK are established,
assert CKE.
• Issue NOPs for tXSRD cycles.
• Issue ZQCL to each rank.
• The global scheduler will be enabled to issue commands.