Hub Datasheet

96 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.6.28 SERRCMD_DRAM—SEER Command Register (D0:F1)
Address Offset: 8Ch
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SERR will be generated when the associated flag is set in the
DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Registers, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
3.6.29 DRAM_CELOG_ADD—DRAM First Correctable Memory
Error Address Register (D0:F1)
Address Offset: A0–A3h
Default Value: 0000 0000h
Sticky Yes
Attribute: RO
Size: 32 bits
This register contains the address of the first correctable memory error. This register is locked
when bits in either the DRAM_FERR or DRAM_NERR Registers are set. If the bits in both
registers are set to 0, the DRAM_CELOG_ADD can be updated; however, if a bit in either register
is set to 1, then DRAM_CELOG_ADD will retain its value for logging purposes. This register is
only valid if a bit in either the DRAM_FERR or DRAM_NERR Register is set.
Bits
Default,
Access
Description
7:2 Reserved
1
0b
R/W
SERR on Multiple-Bit DRAM ECC Error (DMERR).
0 = Disable.
1 = Enable. The MCH generates an SERR when it detects a multiple-bit error reported
by the DRAM controller.
0
0b
R/W
SERR on Single-Bit DRAM ECC Error (DSERR).
0 = Disable.
1 = Enable. The MCH generates an SERR when the DRAM controller detects a single-
bit error.
Bits
Default,
Access
Description
31:28 Reserved
27:6
0000h
RO
CE Address. This field contains address bits 33:12 of the first correctable memory error.
The address bits are a physical address.
5:0 Reserved