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Intel

E7505 Chipset MCH Datasheet 85

3.6.13 NERR_GLOBAL—Global Next Error Register (D0:F1)

Address Offset: 44–47h

Default Value: 0000 0000h

Sticky Yes

Attribute: RO, R/WC

Size: 32 bits

The FIRST global error will be stored in FERR_GLOBAL. This register stores all future global

errors. Multiple bits in this register may be set.

Note: To prevent the same error from being logged twice in FERR_GLOBAL and NERR_GLOBAL, a

FERR_GLOBAL bit being set blocks the respective bit in the NERR_GLOBAL Register from

being set. In addition, bits [18:16] are grouped such that if any of these bits are set in the

FERR_GLOBAL Register, none of the bits [18:16] can be set in the NERR_GLOBAL Register.

For example, if HI_A causes its respective FERR_GLOBAL bit to be set, any subsequent DDR,

FSB, or HI_A error will not be logged in the NERR_GLOBAL Register. Each of these three bits

are part of Device 0 status and having any one of them set in FERR_GLOBAL represents a

"Device 0 First Error" occurred. This implementation blocks logging in NERR_GLOBAL of any

subsequent "Device 0" errors, and allows only logging of subsequent errors that are from other

devices.

Note: Software must write a 1 to clear bits that are set.

Bits

Default,

Access

Description

31:19 Reserved

R/WC

DRAM Interface Error Detected.

0 = No DRAM interface error detected.

1 = The MCH has detected an error on the DRAM interface.

R/WC

HI_A Error Detected.

0 = No HI_A interface error detected.

1 = The MCH has detected an error on the HI_A.

R/WC

System Bus Error Detected.

0 = No system bus interface error detected.

1 = The MCH has detected an error on the System Bus.

15:3 Reserved

R/WC

HI_B Error Detected.

0 = No HI_B interface error detected.

1 = The MCH has detected an error on HI_B.

1:0 Reserved