Hub Datasheet
70 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.26 ACAPID—AGP Capability Identifier Register (D0:F0)
Address Offset: A0–A3h
Default Value: 0030 0002h
Attribute: RO
Size: 32 bits
This register provides the standard identifier for AGP capability. Read by drivers.
3.5.27 AGPSTAT—AGP Status Register (D0:F0)
Address Offset: A4–A7h
Default Value: See table below
Attribute: RO
Size: 32 bits
This register reports AGP device capability/status. Read by drivers.
Bits
Default,
Access
Description
31:24 Reserved
23:20
3h
RO
Major AGP Revision Number (MAJREV). These bits provide a major revision
number of AGP specification to which this version of MCH conforms. This field is
hardwired to value of 0011b (i.e., implying AGP Specification 3.0).
19:16
0h
RO
Minor AGP Revision Number (MINREV). These bits provide a minor revision number
of AGP specification to which this version of MCH conforms. This number is hardwired
to value of 0000 which implies that the revision is x.0. Together with major revision
number this field identifies the MCH as an AGP Specification 2.0 compliant device.
15:8
00h
RO
Next Capability Pointer (NCAPTR). AGP capability is the first and the last capability
described via the capability pointer mechanism and therefore these bits are hardwired
to 0s to indicate the end of the capability linked list.
7:0
02h
RO
AGP Capability ID (CAPID). This field identifies the linked list item as containing AGP
registers. This field has a value of 0000_0010b assigned by the PCI SIG.
Bits
Default,
Access
Description
31:24
1Fh
RO
Request Queue (RQ). Hardwired to 1Fh. This field contains the maximum number of
AGP command requests the MCH is configured to manage.
1Fh =32 outstanding AGP command requests maximum can be handled by the MCH.
23:16 Reserved
15:13
010b
RO
Async Request Size. This value is LOG2 of the optimum asynchronous request size
in bytes minus 4 to be used with the MCH.
2h = 64 byte MCH cache line size.
12:10
000b
RO
MCH Bus Period for I/O Buffer Calibration.
000 = 4 ms
9
1b
RO
Side Band Addressing Support (SBA). Hardwired to 1. The MCH supports side
band addressing.
8:7 Reserved
6
0
RO
Host Translation Support (HTRANS#). Hardwired to 0. The MCH supports
translating accesses from the host processor through the aperture.