Hub Datasheet

66 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.21 REROTC—Receive Enable Reference Output Timing
Control Register (D0:F0)
Address Offset: 80–81h
Default Value: 0000h
Attribute: R/W
Size: 16 bits
3.5.22 CLOCK_DIS—CK/CK# Clock Disable Register (D0:F0)
Address Offset: 8Ch
Default Value: FFh
Attribute: R/W
Size: 8bit
Bits
Default,
Access
Description
15
0b
R/W
Increase Read/Write Turnaround Margin. Total turnaround margin is controlled by this
field in addition to the back-to-back read write turnaround control (bit 28) of the DRAM
Timing Register. It is expected that extra margin will be required for 266 MHz DDR
operation with CAS Latency of 2.5 and would increase the total delay between
commands to 6 clocks from 5.
0 = No extra turnaround margin between read and write cycles.
1 = Add 1 DCLK of turnaround margin between read and write cycles.
14:0 Reserved
Bits
Default,
Access
Description
7:0
FFh
R/W
CK/CK# Disable. Each bit corresponds to a CK/CK# pair of pins on each channel.
Bit 0 corresponds to CK0 and CK0# while bit 5 corresponds to CK5 and CK5#. When
set to 1, these bits turn off the corresponding CK/CK# pair on both channels. CK is
driven low and CK# is driven high. This feature is intended to reduce EMI due to
clocks toggling to DIMMs which are not populated.
The table below shows how the clock pins are used on the two main motherboard
types
.
Bit Pins Registered Unbuffered MB
7
CMDCLK x7
CMDCLK x7#
Not Used. Pins become
chip selects
DIMM1 CK2/CK2#
6
CMDCLK x6
CMDCLK x6#
Not Used. Pins become
chip selects
DIMM0 CK2/CK2#
5
CMDCLK x5
CMDCLK x5#
Not Used DIMM1 CK1CK1#
4
CMDCLK x4
CMDCLK x4#
Not Used DIMM0 CK1/CK1#
3
CMDCLK x3
CMDCLK x3#
DIMM3 CK0/CK0# Not Used
2
CMDCLK x2
CMDCLK x2#
DIMM2 CK0/CK0# Not Used
1
CMDCLK x1
CMDCLK x1#
DIMM1 CK0/CK0# DIMM1 CK0CK0#
0
CMDCLK x0
CMDCLK x0#
DIMM0 CK0/CK0# DIMM0 CK0CK0#