Hub Datasheet

62 Intel
®
E7505 Chipset MCH Datasheet
Register Description
26:24
000b
R/W
Read Delay (t
RD
). This t
RD
value represents the time elapsed from the internal DCLK
rising (for which command is sent) until HCLK rising for which initial SB data is driven
(and the data can be read from the DDR receive FIFO).
23:19 Reserved
18:16
000b
R/W
DRAM Idle Timer. This field determines the number of clocks the DRAM controller will
remain in the idle state before it begins precharging all pages.
000 = Infinite
001 = 0
010 = 8 DRAM clocks
011 = 16 DRAM clocks
100 = 64 DRAM clocks
Others = Reserved
15:11 Reserved
10:9
00b
R/W
Activate to Precharge delay (t
RAS
). This bit controls the number of DRAM clocks for
t
RAS.
00 = 7 Clocks
01 = 6 Clocks
10 = 5 Clocks
11 = Reserved
8:6 Reserved
Bits
Default,
Access
Description
Parameter Min Max
DCLK to CK rising 5 ns 5 ns
CAS Latency 15 ns 25 ns
DIMM type 0 ns 10 ns
CH DLY 0 ns 10 ns
t
PD
0 ns 10 ns
Even Odd arrival 5 ns 5 ns
t
RD
(Round number to integer number) 30 ns 70 ns
CAS# Latency Registered DIMM Unbuffered DIMM
t
RD
min t
RD
max t
RD
min t
RD
max
25746
2.5 5 7 4 7
E
nco
di
ng
t
RD
100
MH
z
t
RD
133
MH
z
Cl
oc
k
s
000 70 ns 52.5 ns 7
001 60 ns 45 ns 6
010 50 ns 37.5 ns 5
011 40 ns 30 ns 4
100 30 ns 22.5 ns 3
101 80 ns 60 ns 8
110 90 ns 67.5 ns 9
111 reserved reserved reserved