Hub Datasheet

48 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.4 PCISTS—PCI Status Register (D0:F0)
Address Offset: 06–07h
Default Value: 0090h
Attribute: RO, R/WC
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. Bit 14 is read/write clear. All other bits are Read Only. Since MCH Device 0 does not
physically reside on PCI_A many of the bits are not implemented.
Note: Software must write a 1 to clear bits that are set.
Bits
Default,
Access
Description
15
0b
R/WC
Detected Parity Error (DPE).
0 = No Parity error detected.
1 = MCH detected an address or data parity error on the HI_A interface.
14
0b
R/WC
Signaled System Error (SSE).
0 = No SERR generated by MCH Device 0.
1 = MCH Device 0 generated an SERR message over HI_A for an enabled Device 0
error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD
registers. Device 0 error flags are read/reset from the PCISTS or Error registers.
13
0b
RO
Received Master Abort Status (RMAS). Hardwired to 0. The Intel
®
ICH4 will never
send a Master Abort completion on HI_A.
12
0b
R/WC
Received Target Abort Status (RTAS).
0 = No received Target Abort generated by MCH.
1 = MCH generated a HI_A request that receives a Target Abort completion packet.
11
0b
RO
Signaled Target Abort Status (STAS). Hardwired to 0. The MCH will not generate a
Target Abort HI_A completion packet.
10:9
00b
RO
DEVSEL Timing (DEVT). Hardwired to 00. Device 0 does not physically connect to
PCI_A. These bits are set to 00 (fast decode) so that optimum DEVSEL timing for PCI_A
is not limited by the MCH.
8
0b
RO
Master Data Parity Error Detected (DPD). Hardwired to 0. PERR signaling and
messaging are not implemented by the MCH.
7
1b
RO
Fast Back-to-Back (FB2B). Hardwired to 1. Device 0 does not physically connect to
PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the optimum
setting for PCI_A is not limited by the MCH.
6:5 Reserved
4
1b,
RO
Capability List (CLIST). Hardwired to 1. This indicates to the configuration software that
this device/function implements a list of new capabilities. A list of new capabilities is
accessed via register CAPPTR at configuration address offset 34h. Register CAPPTR
contains an offset pointing to the start address within configuration space of this device
where the AGP Capability standard register resides. This bit is always a 1, since the fuse
capability structure exists in all configurations.
3:0 Reserved