Hub Datasheet

Signal Description

38 Intel

E7505 Chipset MCH Datasheet

2.8 Strap Signals

NOTE: HA7# and HA15# are part of the regular system address bus; therefore, they do not require extra pins

for this support.

Pin Strap Name Description

DDR_STRAP

CMOS

DDR Strap Input. This pin is used to indicate to the BIOS the memory

type. This pin should be grounded on a motherboard implementing

registered DDR DIMMs. It should be pulled up to 2.5 V on a motherboard

implementing unbuffered DDR DIMMs.

HA7#

CPU Bus In-

Order Queue

Depth

The value on HA7# is sampled by all processor bus agents, including the

MCH, on the rising edge of CPURST#. Its latched value determines the

maximum IOQ depth mode supported on the processor bus.

• If HA7# is sampled low, the IOQ depth on the bus is one.

• If HA7# is sampled high, the IOQ depth on the bus is the maximum of

12.

This signal is driven by the MCH from the value set by BIOS.

HA15# SB Bus Parking

The value on HA15# is sampled by all processor bus agents, including the

MCH, on the rising edge of CPURST#. A high voltage level will force the

processor(s) into Bus Parking Mode. This signal has no functional affect on

the MCH itself. This signal is driven by the MCH from the value set by

BIOS.

VREF

Compare

AGP Select

The state of the VREF Comparator determines the use of the muxed AGP

signals. The PREF_AGP[1:0] inputs will be at 0.35 V for AGP 3.0 signaling

made, and 0.75 V for AGP 2.0 signaling mode. This level is set by resistors

using the GC_DET# pin on the AGP connector, or from the AGPVREFGC

generated by the graphics card. The VREF Comparator will be 0 for

AGP3.0 signaling mode and a 1 for AGP 2.0 signaling mode

VREF Analog Level Mode

0.35 V AGP 3.0 signaling

0.75 V APG 2.0 signaling