Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 31
Signal Description
CAS_B#
O
SSTL-2
Column Address Strobe: This signal is used to indicate a read or write
command to the open page in the bank specified by the BA_x signals.
CAS_B# is also used to enter register set mode or start an auto refresh or
enter self refresh.
WE_B#
O
SSTL-2
Write Enable: This signal is used to differentiate a read from a write
command when CAS_B# is active and RAS_B# is inactive. It is used to
differentiate an activate command when RAS is active and CAS _B# is
inactive. WE_B# is also used to terminate a burst, enter register set mode.
CKE_B[3:0]
O
SSTL-2
Clock Enable: CKEx high activates and CKEx low deactivates internal
clock signals, and device input buffers and output drivers. Driving CKEx low
provides precharge powerdown and self refresh operation (all banks idle), or
Active Powerdown (row active in any bank). CKEx is synchronous for
powerdown entry and exit, and for self refresh entry. CKEx is asynchronous
for self refresh exit, and for output disable. Input buffers, excluding CK, CK
and CKEx are disabled during powerdown. Input buffers, excluding CKEx
are disabled during self refresh.
The CKEx signals are driven low when the RSTIN# signal is low to keep the
DRAMs in self refresh mode.
Registered: One for even rows, one for odd rows. Unbuffered: One per row.
RCVENOUT_B#
O
SSTL-2
Receive Enable Output: This signal is driven low and fed back internally
when the DQ bus is to receive data (DRAM reads). Used to set the timing for
enabling the DQS input buffers so that they are enabled only when driven by
the DRAMs. This signal must be terminated externally.
DVREF_B
I
Analog
Voltage Reference.
DRCOMP_V
I/O
SSTL-2
Compensation for DDR Vertical Direction: This signal is used to calibrate
the DDR buffers. It is used for both channels on the vertical direction buffers.
Externally, it is connected to a 25 Ω resistor to ground.
DRCOMPVREF_V Analog
RComp VREF: This signal is used for both channels on the vertical direction
buffers. This pin is connected to an external voltage derived from a resistor
network.
Table 2-3. DDR Channel B Signals (Sheet 3 of 3)
Signal Name Type Description
Signal 2 DIMM MB 3 DIMM MB
CKE_B3 DIMM 1 CKE1
CKE_B2 DIMM 1 CKE0
CKE_B1 DIMM 0 CKE1 All DIMMs CKE1
CKE_B0 DIMM 0 CKE0 All DIMMs CKE0