Hub Datasheet

170 Intel

E7505 Chipset MCH Datasheet

Functional Description

5.7.1 Processor States

C0 (Full On)

This is the only state that runs software. All clocks are running, STPCLK# is deasserted and the

processor core is active. The processor can service snoops and maintain cache coherency in this

state.

C1 (Auto-Halt)

The first level of power reduction occurs when the processor executes an Auto-Halt instruction.

This stops the execution of the instruction stream and greatly reduces the processors power

consumption. The processor can service snoops and maintain cache coherency in this state. The

MCH is completely oblivious to this processor state.

C2 is not supported by the MCH.

C3 is not supported by the MCH.

5.7.2 Suspend States

S0 (Awake)

In this state all power planes are active. All of the ACPI software “C” states are embedded in this

state.

S1 (Powered-on-Suspend)

The MCH implements a desktop S1 that simply puts the processor in stop-grant mode which is

functionally identical as C2.

S3 (Suspend-to-RAM)

The final level of power savings for the MCH is achievable when the host clock, memory group,

and I/O clock group clocks are shutdown and the MCH is powered down. This occurs when the

system transitions to the S3 State. The MCH places all of the DRAM components into the Power-

down State so that they will perform self-refresh.

S4 (Suspend-to-Disk), S5 (Soft-Off) State

The MCH does not distinguish between Suspend-to-Ram (S3), Suspend-to-Disk (S4), and Soft-Off

(S5) states. From the MCH perspective, entry and exit to S4 or S5 states, is the same as entry and

exit to S3 state.