Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 105
Register Description
3.7.11 PBUSN1—Primary Bus Number Register (D1:F0)
Address Offset: 18h
Default Value: 00h
Attribute: RO
Size: 8 bits
This register identifies that virtual PCI-to-PCI bridge is connected to bus #0.
3.7.12 SBUSN1—Secondary Bus Number Register (D1:F0)
Address Offset: 19h
Default Value: 00h
Attribute: RO, R/W
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI
bridge (i.e., to AGP). This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to AGP.
3.7.13 SUBUSN1—Subordinate Bus Number Register (D1:F0)
Address Offset: 1Ah
Default Value: 00h
Attribute: R/W
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to AGP.
Bits
Default,
Access
Description
7:0
00h
RO
Primary Bus Number (BUSN). Configuration software typically programs this field with
the number of the bus on the primary side of the bridge. Since device 1 is an internal
device and its primary bus is always 0, these bits are read only and are hardwired to
00h.
Bits
Default,
Access
Description
7:0
00h
R/W
Secondary Bus Number (BUSN). This field is programmed by configuration software
with the bus number assigned to AGP.
Bits
Default,
Access
Description
7:0
00h
R/W
Subordinate Bus Number (BUSN). This register is programmed by configuration
software with the number of the highest subordinate bus that lies behind the device 1
bridge. When only a single PCI device resides on the AGP segment, this register
contains the same value as the SBUSN1 register.