Specification Update

12 Intel

E7320 Memory Controller Hub (MCH) Specification Update

Errata

Implication: A spurious error is flagged, and accesses between 4 GB and 32 GB will not succeed in the 32 GB

(maximum) memory configuration, which can result in a system hang.

Workaround: Refer to your Intel representative for details the Intel

E7520, E7320, and E7525 Memory

Controller Hub (MCH) Components BIOS Specification for details.

Status: For the steppings effected, see the Summary Table of Changes.

10. MCH hang on PCI Express enhanced configurations to non-existent devices

causes hang

Problem: A system hang may occur when writing or reading to offsets above 0x0FF using the PCI Express

enhanced configuration space of a non-existent device.

Implication: An invalid access error will be flagged, and a system hang may result.

Workaround: Polling or testing for devices must be done using offsets below 0x0FF. Access must not be issued

to offsets above 0x0FF unless the targeted device is confirmed present.

Status: For the steppings effected, see the Summary Table of Changes.

11. Spurious errors logged during link training events

Problem: The MCH reports spurious receiver errors during initial link training, after a retrain, or after a

secondary bus reset has occurred.

Implication: Spurious receiver errors will be logged in the associated port. There are no negative side effects

besides the misreported error.

Workaround: Upon initial training and after each retrain or secondary bus reset, clear the correctable error

detected bit of the PCI Express Device Status register (EXP_DEVSTS, Device 2-3, Function 0,

Offset 6E-6Fh bit 0, 1b) and the receiver error status bit of the PCI Express Correctable Error

Status register (EXP_CORERRSTS, Device 2-3, Function 0, Offset 110-113h bit 0, 1b). Also clear

the FERR/NERR bits that flag correctable errors (EXP_FERR/EXP_NERR, Device 2-3, Function

0, Offset 160-163h / 164-167h bit 6, 1b).

Status: For the steppings effected, see the Summary Table of Changes.

12. DDR2 write offset issue

Problem: DQ/DQS signals terminate to a level about 300mv below VDDQ/2 between write bursts. No

functional failures have been observed as a function of this issue.

Implication: Signal integrity issues may be observed.

Workaround: None

Status: For the steppings effected, see the Summary Table of Changes.

13. HiLoCS bit not readable in memory error address registers

Problem: In the Error Address registers, bit 0 (HiLoCS) is not accessible via software and will always return

0b if read.

The affected registers are:

DRAM_SEC1_ADD D0:F1:A0-A3h

DRAM_DED_ADD D0:F1:A4-A7h