Vol 2

Processor Uncore Configuration Registers
176 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.7.3.3 DRAM_ENERGY_STATUS
DRAM energy consumed by all the DIMMS in all the Channels. The counter will wrap
around and continue counting when it reaches its limit.
The energy status is reported in units which are defined in
DRAM_POWER_INFO_UNIT_MSR[ENERGY_UNIT].
The data is updated by PCU microcode and is Read Only for all SW.
13.7.3.4 DRAM_ENERGY_STATUS_CH[0:3]
DRAM energy consumed by all the DIMMS in ChannelX (X = 0, 1, 2, 3). The counter will
wrap around and continue counting when it reaches its limit.
The data is updated by PCU microcode and is Read Only for all SW.
13.7.3.5 DRAM_RAPL_PERF_STATUS
This register is used by PCU microcode to report DRAM Plane Power limit violations in
the Platform PBM.
30:16 RW_L 0x78
Minimal DRAM Power (DRAM_MIN_PWR):
The minimal power setting allowed for DRAM. Lower values will be clamped to
this value. The minimum setting is typical (not guaranteed).
The units for this value are defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
15:15 RV - Reserved.
14:0 RW_L 0x118
Spec DRAM Power (DRAM_TDP):
The Spec power allowed for DRAM. The TDP setting is typical (not guaranteed).
The units for this value are defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 2
Offset: 0x90
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 2
Offset: 0xa0
Bit Attr Default Description
31:0 RO_V 0x0
Energy Value (DATA):
Energy Value
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 2
Offset: 0xa8, 0xb0, 0xb8, 0xc0
Bit Attr Default Description
31:0 RO_V 0x0
Energy Value (DATA):
Energy Value