Vol 1

Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family 19
Datasheet Volume One, February 2014
Overview
Jitter Any timing variation of a transition edge or edges from the defined Unit Interval
(UI).
IOV I/O Virtualization
LGA2011-1 Socket The 2011-0 land FCLGA package mates with the system board through this
surface mount, 2011-0 contact socket.
LLC Last Level Cache
LRDIMM Load Reduced Dual In-line Memory Module
NCTF Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
NEBS Network Equipment Building System. NEBS is the most common set of
environmental design guidelines applied to telecommunications equipment in the
United States.
PCH Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCU Power Control Unit
PCI Express* 3.0 The third generation PCI Express* specification that operates 60% faster than
PCI Express* 2.0 (8 GB/s); however, PCI Express* 3.0 is completely backward
compatible with PCI Express* 1.0 and 2.0.
PCI Express 3.0 PCI Express* Generation 3.0
PCI Express 2.0 PCI Express* Generation 2.0
PCI Express 1.0 PCI Express* Generation 2.0/3.0
PECI Platform Environment Control Interface
Phit Physical Unit. An Intel® QPI terminology defining units of transfer at the physical
layer. 1 Phit is equal to 20 bits in ‘full width mode’ and 10 bits in ‘half width
mode’
Processor The 64-bit, single-core or multi-core component (package)
Processor Core The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
RDIMM Registered Dual In-line Module
Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a
DDR3 DIMM.
Intel® Xeon® E7 v2
Processor
Intel® Xeon® E7 v2 processor supports scalable server and HPC platforms for
two or more processors, including glueless four-way and glueless eight-way
platforms.
Scalable-2S,4S, 8S Targeted for scalable designs, including those using third party Node Controller
chips. In these designs, Node Controller is used to scale the design beyond
two/four/eight sockets.
SCI System Control Interrupt. Used in ACPI protocol.
SSE Intel® Streaming SIMD Extensions (Intel® SSE)
SKU A processor Stock Keeping Unit (SKU) to be installed in either server or
workstation platforms. Electrical, power and thermal specifications for these
SKU’s are based on specific use condition assumptions. Server processors may
be further categorized as Efficient Performance server, workstation and HPC
SKUs. For further details on use condition assumptions, please refer to the latest
Product Release Qualification (PRQ) Report available via your Customer Quality
Engineer (CQE) contact.
SMBus System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the
system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Philips Semiconductor.
Term Description