Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 181
Datasheet Volume One, February 2014
PIROM
9.3.4.13 VTT: VTT
This field contains the voltage requested for the Vtt pins. This field is in mV and is
reflected in hex. Some systems read this offset to determine if all processors support
the same default Vtt settings. Writes to this register have no effect.
Example: A voltage of 1.000 VTT would contain an Offset 43-44h value of 1000h.
9.3.4.14 RES5: Reserved 5
This location is reserved. Writes to this register have no effect.
9.3.5 Package Data
This section contains substrate and other package related data.
9.3.5.1 PREV: Package Revision
This location tracks the highest level package revision. It is provided in an ASCII format
of four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,
2.0, and so forth. If only three ASCII characters are consumed, a leading space is
provided in the data field. Writes to this register have no effect.
Example: The Intel® Xeon® E7 v2 processor utilizes the second revision of the
LGA-2011 package. Thus, at offset 4C-4F-35h, the data is a space followed by 2.0. In
hex, this would be 20h, 32h, 2Eh, 30h.
Offset: 43h-44h
Bit Description
15:0 Cache Voltage ID
0000h-FFFFh: mV
Offset: 45-46h
Bit Description
15:0 Cache Voltage Tolerance, High
0000h-FFFFh: mV
Offset: 47h-4Bh
Bit Description
39:0 RESERVED
0000000000h-FFFFFFFFFFh: Reserved