Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 179
Datasheet Volume One, February 2014
PIROM
Example: The Intel® Xeon® E7 v2 processor supports a maximum Intel SMI2
performance transfer rate of 2.666 GT/s. Therefore, offset 33h-34h has a value
of 2666h.
9.3.4.6 MAXSML: Maximum Intel SMI2 Lock Step Transfer Rate
Systems may need to read this offset to decide on compatible processors and Intel
C102/C104 Scalable Memory Buffer capabilities. The data provided is the transfer rate,
rounded to a whole number, and reflected in binary coded decimal. Writes to this
register have no effect.
Example: The Intel® Xeon® E7 v2 processor supports a maximum Intel SMI 2 lock
step transfer rate of 1.600 GT/s. Therefore, offset 33h-34h has a value of 1600h.
9.3.4.7 MXSAVD: MAX VSA VID
Offset 37h-38h is the Processor Vsa maximum VID (Voltage Identification) field and
contains the maximum voltage requested via the VID pins. This field, rounded to the
next thousandth, is in mV and is reflected in binary coded decimal. Some systems read
this offset to determine if all processors support the same default VID setting. Writes to
this register have no effect.
Example: A voltage of 1.200 V maximum core VID would contain 1200h in Offset
36- 37h.
9.3.4.8 MNSAVD: MIN VSA VID
Offset 39h-4Ah is the Processor Vsa minimum VID (Voltage Identification) field and
contains the minimum voltage requested via the VID pins. This field, rounded to the
next thousandth, is in mV and is reflected in binary coded decimal. Some systems read
this offset to determine if all processors support the same default VID setting. Writes to
this register have no effect.
Example: A voltage of 0.600 V maximum core VID would contain 600h in Offset
39- 4Ah.
Offset: 33h-34h
Bit Description
15:0 Maximum Intel SMI Transfer Rate
0000h-FFFFh: MHz
Offset: 35h-36h
Bit Description
15:0 Minimum Intel SMI Transfer Rate
0000h-FFFFh: MHz
Offset: 37h-38h
Bit Description
15:0 MAX VSA VID
0000h-FFFFh: mV