Update

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Intel

Xeon

Processor E7-8800/4800/2800 Product Families 37

Specification Update November 2014

Documentation Changes

The Documentation Changes listed in this section apply to the following documents:

• Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic

Architecture.

• Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:

Instruction Set Reference Manual A-M.

• Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:

Instruction Set Reference Manual N-Z.

• Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:

System Programming Guide.

• Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:

System Programming Guide.

All Documentation Changes will be incorporated into a future version of the appropriate

Processor documentation.

Note: Documentation changes for Intel

64 and IA-32 Architecture Software Developer’s

Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel

and IA-32 Architecture Software Developer’s Manual Documentation Changes. Follow

the link below to become familiar with this file.

http://developer.intel.com/products/processor/manuals/index.htm

DC1. On-Demand Clock Modulation Feature Clarification

Software Controlled Clock Modulation section of the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3B: System Programming Guide will be modified

to differentiate on-demand clock modulation feature on different processors. The

clarification will state:

For Intel® Hyper-Threading Technology enabled processors, the

IA32_CLOCK_MODULATION register is duplicated for each logical processor. In

order for the on-demand clock modulation feature to work properly, the feature

must be enabled on all the logical processors within a physical processor. If the

programmed duty cycle is not identical for all the logical processors, the processor

clock will modulate to the highest duty cycle programmed for processors with any

of the following CPUID DisplayFamily_DisplayModel signatures [listed in Table 8].

For all other processors, if the programmed duty cycle is not identical for all logical

processors in the same core, the processor will modulate at the lowest programmed

duty cycle.

For multiple processor cores in a physical package, each core can modulate to a

programmed duty cycle independently.

For the P6 family processors, on-demand clock modulation was implemented

through the chipset, which controlled clock modulation through the processor’s

STPCLK# pin.

Table 7. CPUID DisplayFamily_DisplayModel Signatures for Legacy Processors That

Resolve to Higher Performance Setting of Conflicting Duty Cycle Requests

06_1A

06_1C

06_1E

06_1F

06_25

06_26

06_27

06_2C

06_2E

06_2F

06_35

06_36

0F_xx