Specification Update
8 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
Identification Information
The Intel
®
Xeon
®
Processor 7000 Series can be identified by the following register
contents:
NOTES:
1. The Extended Family corresponds to bits [27:20] of the EDX register after RESET, bits [27:20] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation
field of the Device ID register accessible through Boundary Scan.
2. The Extended Model corresponds to bits [19:16] of the EDX register after RESET, bits [19:16] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of
the Device ID register accessible through Boundary Scan.
3. The Type corresponds to bits [13:12] of the EDX register after RESET, bits [13:12] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
4. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
5. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after
the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register. Please
refer to the AP-485 Intel
®
Processor Identification and the CPUID Instruction
Application Note for further information on the CPUID instruction.
NOTES:
1. These parts have PROCHOT# enabled
2.These parts have THERMTRIP# enabled
3.These parts are enabled for Enhanced Intel SpeedStep® Technology (EIST).
4.These parts are enabled for Enhanced Halt State (C1E).
5.These parts are enabled with Hyper-Threading Technology.
6.These parts are enabled with Execute Disable Bit (NX).
7.These parts are enabled for Intel® Extended Memory 64 Technology.
8.These parts are enabled with Intel® Virtualization Technology (VT).
Extended Family
1
Extended Model
2
Type
3
Family
4
Model
5
00000000b 0000b 00b
1111b 0100b
Table 1. Intel
®
Xeon
®
Processor 7000 Series Identification Information
QDF/
S-Spec
Core
Stepping
L2 Cache
Size (bytes)
CPUID
Core
Freq
(GHz)
Data Bus
Freq
(MHz)
Package and Revision Notes
SL8UC A0 2M x 2 00000F48h 3.0 667 604-pin micro-PGA with 53.3 x
53.3 mm FC-PGA4 package
1, 2, 3, 4,
5, 6, 7, 8
SL8UA A0 1M x 2 00000F48h 2.66 667 604-pin micro-PGA with 53.3 x
53.3 mm FC-PGA4 package
1, 2, 3, 4,
5, 6, 7, 8
SL8UD A0 2M x 2 00000F48h 3.0 800 604-pin micro-PGA with 53.3 x
53.3 mm FC-PGA4 package
1, 2, 3, 4,
5, 6, 7, 8
SL8UB A0 1M x 2 00000F48h 2.8 800 604-pin micro-PGA with 53.3 x
53.3 mm FC-PGA4 package
1, 2, 3, 4,
5, 6, 7, 8