Specification Update

Intel
®
Xeon
®
Processor 7000 Series 37
Specification Update, March 2010
Status: For the steppings affected, see the Summary Table of Changes.
A71. VM exit due to TPR shadow below threshold may improperly set and
cause “Blocking by STI” actions
Problem: In a system supporting Intel Virtualization Technology and Intel EM64T, the “blocking
by STI” bit of the interruptibility-state field may be saved as 1 rather than 0. This
erratum may occur when a STI instruction is executed directly prior to a MOV to CR8
which results in a VM exit due to a reduction of the TPR shadow value below the TPR
threshold.
Implication: When this erratum occurs, delivery of an interrupt may be delayed by one instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A72. VM exit on Load Machine Status Word (LMSW) may not show expected
exit information in the Virtual-Machine Control Structure (VMCS)
Problem: In systems supporting Intel Virtualization Technology, a VM exit
on an LMSW instruction, which references memory, may not return expected exit
information concerning data breakpoints in the VMCS.
Implication: When this erratum occurs, VMM software may not be able to recognize and handle data
breakpoints for the LMSW instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A73. A VM exit may occur when the processor is in wait-for-SIPI or
shutdown states and a chipwide power down transition occurs
Problem: In a system supporting Intel Virtualization Technology, the processor may incorrectly
VM exit under the following conditions:
• Interrupt-Window-Exiting VM-execution control is set
•RFLAGS[IF]=1
• Chipwide power down transition requests occur when the processor is in Wait-For-
SIPI or Shutdown states.
Implication: Due to this erratum, Interrupt-Window-Exiting VM exits may take the logical
processor out of Wait-For-SIPI and Shutdown states. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A74. The execution of a VMPTRLD instruction may cause an unexpected
memory access
Problem: In a system supporting Intel Virtualization Technology, executing VMPTRLD may cause
a memory access to an address not referenced by the memory operand.
Implication: This erratum may cause unpredictable system behavior or system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A75. The execution of VMPTRLD or VMREAD may cause an unexpected
memory access
Problem: On processors supporting Intel Virtualization Technology, executing a VMPTRLD or a
VMREAD instruction outside of VMX mode may result in a load to an unexpected
address.