Specification Update

36 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A67. The processor may incorrectly respond to machine checks during VM
entry/exit transitions
Problem: In systems supporting Intel Virtualization Technology, when machine checks are
encountered during VM entry/exit transitions, the processor is expected to respond
with a VM exit (if a machine check occurs during VM entry) or abort (if a machine check
occurs during VM exit). As a result of this erratum when machine checks occur
during VM entry/exit transitions the processor will attempt to service the machine
check which may lead to IERR-shutdown or execution of the Machine Check handler,
dependent on the CR4.MCE setting.
Implication: The system may end up in the shutdown state if CR4.MCE is not set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A68. NIT during string operations in the Virtual-Machine Extension (VMX)
guest mode may cause unexpected system behavior
Problem: In a system supporting Intel Virtualization Technology, if INIT occurs during REP LODS/
MOVS/STOS/INS/OUTS while the processor is executing in VMX guest mode, after
servicing the INIT, the host will resume at the next instruction and does not complete
the remainder of string operation.
Implication: This erratum may cause unexpected system behavior to occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A69. Power down requests may not be serviced if a power down transition
is interrupted by an in-target probe event in the presence of a specific
type of VM exit
Problem: In a system supporting Intel Virtualization Technology, the processor may service a
pended VM exit prior to completely exiting out of a low power state when the following
sequences of events occur:
• Chip-wide power down transition occurs, and
• VM exit due to a VMLaunch, VMResume, STI, POPF, POPFD, or IRET instruction is
pended, and
• Chip-wide power down transition is interrupted by an in-target probe event.
Implication: Due to this erratum the processor may not recognize further STPCLK# assertions, TM1,
TM2, or Enhanced Intel SpeedStep
®
Technology. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A70. VM entry/exit writes to LSTAR/SYSCALL_FLAG MSRs may cause
incorrect data to be written to bits [63:32]
Problem: Incorrect MSR data in bits [63:32] may be observed in the following two cases:
1. When ECX contains 0xC0000084 and a VM entry/exit writes the IA32_CR_LSTAR
MSR (MSR Address 0xC0000082) bits [63:32] of the data may be zeroed.
2. When ECX does not contain 0xC0000084 and a VM entry/exit writes the
IA32_CR_SYSCALL_FLAG_MASK MSR (MSR Address 0xC0000084) bits [63:32] of
the data may not be zeroed.
Implication: Bits [63:32] of the affected MSRs may contain the wrong data after a VM exit/entry
which loads the affected MSR.
Workaround: None identified.