Specification Update

Intel
®
Xeon
®
Processor 7000 Series 35
Specification Update, March 2010
A62. VM exit on Load Machine Status Word (LMSW) may not show expected
exit information in the Virtual-Machine Control Structure (VMCS)
Problem: In systems supporting Intel Virtualization Technology, a VM exit
on an LMSW instruction, which references memory, may not return expected exit
information concerning data breakpoints in the VMCS.
Implication: When this erratum occurs, Virtual-Machine Monitor (VMM) software may not be able
to recognize and handle data breakpoints for the LMSW instruction
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A63. An incorrect load may be issued under conditions which cause VM exit
Problem: In systems supporting Intel Virtualization Technology, any condition which causes VM
exit may cause the processor to issue a load to an invalid address if the Virtual Machine
Extension (VMX) operation is configured to run with legacy treatment of SMI Delivery.
Implication: This erratum may cause unpredictable system behavior or system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A64. A Start-up IPI (SIPI) VM exit does not clear pending INITs
Problem: In systems supporting Intel Virtualization Technology, a SIPI initiated VM exit does not
clear pending INITs.
Implication: Pending INITs will be serviced upon the return to the guest.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A65. Access to an unsupported address range in uniprocessor (UP) or dual
processor (DP) systems supporting Intel® Virtualization Technology
may not trigger appropriate actions
Problem: When using processors supporting Intel Virtualization Technology and configured as
dual or single processor-capable (i.e. not multiprocessor-capable), the processor
should perform address checks using a maximum physical address width of 36.
Instead, these processors will perform address checks using a maximum physical
address width of 40.
Implication: Due to this erratum, actions which are normally taken upon detection of an
unsupported address may not occur. Software which does not attempt to access
unsupported addresses will not experience this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A66. VM exit due to a MOV from CR8 may cause an unexpected memory
access
Problem: In a system supporting Intel Virtualization Technology and Intel
®
Extended Memory 64
Technology (Intel
®
EM64T), if the “CR8-store exiting” bit in the processor-based VM-
execution control field is set and the “use TPR shadow” bit is not set, a MOV from CR8
instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit
may generate an unexpected memory access.
Implication: When this erratum occurs, a read access to unexpected address may be issued to the
chipset. Subsequent side effects are dependent on chipset operation and may include
system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.