Specification Update

32 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A49. At core-to-bus ratios of 16:1 and above defer reply transactions with
non-zero REQb Values; may cause a front side bus stall
Problem: Certain processors are likely to hang the front side bus (FSB) if the following conditions
are met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b,
or 111b, and
2. The operating bus ratio is 16:1 or higher.
When these conditions are met, the processor may incorrectly and indefinitely
assert a snoop stall for the Defer Reply transaction. Such an event will block further
progress on the FSB.
Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with
any commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A50. CPUID reports thermal monitor 2 supported when running at ratios
18:1 and above
Problem: When the CPUID instruction is executed on a processor which is running at ratios 18:1
and above, the system incorrectly reports that Thermal Monitor 2 is supported.
Implication: When this erratum occurs, the processor incorrectly reports that Thermal Monitor 2 is
supported.
Workaround: Software should ignore the feature flag on the processor and not use it as an indication
that it can enable Thermal Monitor 2. Note that Thermal Monitor remains a feature and
must be enabled for the processor to remain within specification.
Status: For the steppings affected, see the Summary Table of Changes.
A51. The processor may issue front side bus transactions up to 6 clocks
after RESET# is asserted
Problem: The processor may issue transactions beyond the documented 3 FSB clocks and up to 6
FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where
the chipset asserts RESET# when the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A52. Front side bus machine checks may be reported as a result of on-going
transactions during warm reset
Problem: Processor FSB protocol/signal integrity machine checks may be reported if the
transactions are initiated or in-progress during a warm reset. A warm reset is where
the chipset asserts RESET# when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are
allowed to occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets
which do not block new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary Table of Changes.
A53. Entering single logical processor mode via power on configuration
may not work
Problem: When the system uses power on configuration (POC) to enter single logical processor
mode on a dual core processor (by asserting A31# at the deassertion of RESET#), the