Specification Update

30 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
b. Update the associated cache line state information to shared state on the originating bus
(rather than invalid state) in reaction to a BWIL or BLW.
Status: For the steppings affected, see the Summary Table of Changes.
A41. Control register 2 (CR2) can be updated during a REP MOVS/STOS
instruction with fast strings enabled
Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with
fast strings enabled, it is possible for the value in CR2 to be changed as a result of an
interim paging event, normally invisible to the user. Any higher priority architectural
event that arrives and is handled while the interim paging event is occurring may see
the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel
has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A42. REP STOS/MOVS instructions with RCX >= 2^32 may cause a system
hang
Problem: In IA-32e mode using Intel EM64T-enabled processors, executing a repeating string
instruction with the iteration count greater than or equal to 2^32 and a pending event
may cause the REP STOS/MOVS instruction to live lock and hang.
Implication: When this erratum occurs, the processor may live lock and result in a system hang.
Intel has not observed this erratum with any commercially available software or
system.
Workaround: Do not use strings larger than 4 GB.
Status: For the steppings affected, see the Summary Table of Changes.
A43. An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail
to execute to completion or may write to incorrect memory locations
on processors supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS
instruction executed with the register RCX >= 2^32, may fail to execute to completion
or may write data to incorrect memory locations.
Implication: This erratum may cause an incomplete instruction execution or incorrect data in the
memory. Intel has not observed this erratum with any commercially available software
or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A44. An REP LODSB or an REP LODSD or an REP LODSQ instruction with
RCX >= 2^32 may cause a system hang on processors supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP LODSB or an REP
LODSD or an REP LODSQ instruction executed with the register RCX >= 2^32 may fail
to complete execution causing a system hang. Additionally, there may be no #GP fault
due to the non-canonical address in the RSI register.
Implication: This erratum may cause a system hang on Intel EM64T-enabled platforms. Intel has
not observed this erratum with any commercially available software or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum
Status: For the steppings affected, see the Summary Table of Changes.