Specification Update

28 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
An FXRSTOR instruction executed with 64-bit operand size may signal a General
Protection Fault (#GP) if the FDP or FP instruction pointer (FIP) is in non-canonical
form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended
#GP fault.
Workaround: Software should avoid using non-canonical effective addressing in Intel EM64T enabled
processors. BIOS can contain a workaround for this erratum removing the unintended
#GP fault on FXRSTOR.
Status: For the steppings affected, see the Summary Table of Changes.
A34. A push of esp that faults may zero the upper 32 bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode,
the processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this
erratum, this instruction fault may change the contents of RSP. This erratum has not
been observed in commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A35. Enhanced halt state (C1E) may not be entered in a Hyper-Threading
Technology enabled processor
Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event
on an HT Technology enabled system, the processor will not enter C1E until the next
SIPI wakeup event for the second logical processor.
Implication: Due to this erratum, the processor will not enter C1E state.
Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled
prior to issuing the first SIPI to the second logical processor.
Status: For the steppings affected, see the Summary Table of Changes.
A36. Checking of page table base address may not match the address bit
width supported by the platform
Problem: If the page table base address, included in the page map level-4 table, page-directory
pointer table, page-directory table or page table, exceeds the physical address range
supported by the platform (e.g. 36-bit) and it is less than the implemented address
range (e.g. 40-bit), the processor does not check if the address is invalid.
Implication: If software sets such invalid physical address in those tables, the processor does not
generate a page fault (#PF) upon access to that virtual address, and the access results
in an incorrect read or write. If BIOS provides only valid physical address ranges to the
operating system, this erratum will not occur.
Workaround: BIOS must provide valid physical address ranges to the operating system.
Status: For the steppings affected, see the Summary Table of Changes.
A37. IA32_MCi_STATUS MSR may improperly indicate that additional MCA
information may have been captured
Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV
bits of the IA32_MCi_STATUS register may be asserted even though the contents of the
IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC may not correspond to the reported machine-check error, even though
the ADDRV and MISCV are asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.