Specification Update

24 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A17. A write to an APIC register sometimes may appear to have not
occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, e.g. CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any subsequent
instructions are executed. No commercial operating system is known to be impacted by
this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A18. Parity error in the L1 cache may cause the processor to hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible
that the processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A19. Locks and SMC detection may cause the processor to temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical
processor executes a synchronization loop that includes one or more bus locks and is
waiting for release by the other logical processor. If the releasing logical processor is
executing instructions that are within the detection range of the self modifying code
(SMC) logic, then the processor may be locked in the synchronization loop until the
arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may
temporarily stop making forward progress. Intel has not observed this erratum with
any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A20. Incorrect debug exception (#DB) may occur when a data breakpoint is
set on an FP instruction
Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to
obtain data about the FP instruction that are causing the FP event. If a data breakpoint
is set on the instruction causing the FP event, the load in the microcode routine will
trigger the data breakpoint resulting in a Debug Exception.
Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP
instruction. Intel has not observed this erratum with any commercially available
software or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.