Specification Update

22 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
Status: For the steppings affected, see the Summary Table of Changes.
A9. System bus interrupt messages without data and which receive a
hard-failure response may hang the processor
Problem: When a System Bus agent (processor or chipset) issues an interrupt transaction
without data onto the System Bus, and the transaction receives a hard-failure
response, a potential processor hang can occur. The processor, which generates an
inter-processor interrupt (IPI) that receives hard-failure response, will still log the MCA
error event cause as hard-failure, even if the APIC causes a hang. Other processors,
which are true targets of the IPI, will also hang on hard-failure-without-data, but will
not record an MCA hard-failure event as a cause. If a hard-failure response occurs on a
System Bus interrupt message with data, the APIC will complete the operation so as
not to hang the processor.
Implication: The processor may hang.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A10. The processor signals page fault exception (#PF) instead of alignment
check exception (#AC) on an unlocked CMPXCHG8B instruction
Problem: If a page fault exception (#PF) and alignment check exception (#AC) both occur for an
unlocked CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on the (#AC) before the (#PF) will be affected since #PF is
signaled in this case.
Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately,
correct the page fault in the page fault handler and then restart the faulting instruction.
Status: For the steppings affected, see the Summary Table of Changes.
A11. FSW may not be completely restored after page fault on FRSTOR or
FLDENV instructions
Problem: If the FPU operating environment or FPU state (operating environment and register
stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or
4-Gbyte boundary and a #PF or segment limit fault (#GP or #SS) occurs on the
instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might
not be restored. If the fault handler does not restart program execution at the faulting
instruction, stale data may exist in the FSW.
Implication: When this erratum occurs, stale data will exist in the FSW.
Workaround: Ensure that the FPU operating environment and FPU state do not cross 64-Kbyte or 4-
Gbyte boundaries. Alternately, ensure that the page fault handler restarts program
execution at the faulting instruction after correcting the paging problem.
Status: For the steppings affected, see the Summary Table of Changes.
A12. Processor issues inconsistent transaction size attributes for locked
operation
Problem: When the processor is in the page address extension (PAE) mode and detects the need
to set the Access and/or Dirty bits in the page directory or page table entries, the
processor sends an 8 byte load lock onto the System Bus. A subsequent 8 byte store
unlock is expected, but instead a 4 byte store unlock occurs. Correct data are provided
since only the lower bytes change, however external logic monitoring the data transfer
may be expecting an 8-byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.