Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 73

3.5.29 AGPCTRL—AGP Control Register (D0:F0)

Address Offset: B0–B3h

Default Value: 0000 0000h

Attribute: RO, R/W

Size: 32 bits

This register provides for additional control of the AGP interface. Set by drivers

Bits

Default,

Access

Description

31:8 Reserved

R/W

GTLB Enable (GTLBEN).

0 = Disable. The GTLB is flushed by clearing the valid bits associated with each entry.

In this mode of operation all accesses that require translation bypass the GTLB.

All requests that are positively decoded to the graphics aperture force the MCH to

access the translation table in main memory before completing the request.

Translation table entry fetches will not be cached in the GTLB. When an invalid

translation table entry is read, this entry will still be cached in the GTLB (ejecting

the least recently used entry).

1 = Enable. Normal operations of the Graphics Translation look aside Buffer.

NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs);

however, the completion of the configuration write that asserts or deasserts

this bit will be delayed pending a complete flush of all dirty entries from the

write buffer. This delay will be incurred because this bit is used as a

mechanism to signal the chipset that the graphics aperture translation table is

about to be modified or has completed modifications. In the first case, all dirty

entries need to be flushed before the translation table is changed. In the

second case, all dirty entries need to be flushed because one of them is likely

to be a translation table entry which must be made visible to the GTLB by

flushing it to memory.

6:0 Reserved