Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 7
4.4 Memory Re-claim Background ..........................................................................154
4.4.1 Memory Re-mapping............................................................................ 154
5 Functional Description.........................................................................................155
5.1 System Bus Overview .......................................................................................155
5.1.1 Source Synchronous Transfers............................................................155
5.1.2 IOQ (In Order Queue) Depth................................................................155
5.1.3 OOQ (Out of Order Queue) Depth .......................................................155
5.1.4 Dynamic Bus Inversion.........................................................................156
5.1.5 System Bus Interrupt............................................................................156
5.2 Hub Interface_A (HI_A) .....................................................................................157
5.3 Hub Interface_B (HI_B) .....................................................................................157
5.4 AGP 8x Interface ...............................................................................................158
5.4.1 Selecting between AGP 3.0 and AGP 2.0 Signaling Modes ................158
5.4.2 Dynamic Bus Inversion (DBI) ...............................................................158
5.4.3 AGP 3.0 and AGP 2.0 Signaling Mode Differences .............................159
5.4.4 AGP 3.0 Downshift (4x data rate) Mode...............................................160
5.4.5 AGP Target Operations........................................................................161
5.4.6 Coherency ............................................................................................161
5.4.7 AGP Aperture and GART .....................................................................162
5.4.8 Peer-to-Peer Traffic..............................................................................162
5.4.9 AGP Electrical Characteristics .............................................................162
5.4.10 AGP 3.0 Protocol..................................................................................163
5.4.11 AGP 2.0 Protocol..................................................................................163
5.4.12 Fast Writes ...........................................................................................164
5.4.13 AGP Connector ....................................................................................164
5.4.14 PCI Semantic Transactions on AGP ....................................................164
5.5 Main Memory Interface...................................................................................... 165
5.5.1 Frequency and Bandwidth....................................................................166
5.5.2 Memory Operation................................................................................166
5.5.3 DRAM Technologies and Types Supported .........................................167
5.5.4 Memory Capacity ................................................................................. 167
5.5.5 Refresh.................................................................................................167
5.5.6 Intel
®
x4 SDDC Technology ECC ........................................................168
5.5.7 Memory Thermal Management ............................................................168
5.5.8 Clock Generation.................................................................................. 168
5.6 System Manageability Bus 2.0 ..........................................................................169
5.7 Power Management ..........................................................................................169
5.7.1 Processor States ..................................................................................170
5.7.2 Suspend States ....................................................................................170
5.7.3 Clock Control........................................................................................171
5.8 Clocking............................................................................................................. 171
5.9 System Reset and Power Sequencing..............................................................171
6 Electrical Characteristics....................................................................................173
6.1 Absolute Maximum Ratings...............................................................................173
6.2 Power Characteristics .......................................................................................173
6.3 I/O Interface Signal Groupings ..........................................................................175
6.4 DC Characteristics ............................................................................................177