Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 29

Signal Description

2.3 DDR Channel B Signals

Table 2-3. DDR Channel B Signals (Sheet 1 of 3)

Signal Name Type Description

CB_B[7:0]

I/O

SSTL-2

ECC Data bits: These signals are the 8-bit ECC data, running at 2x data

rate. The data is source synchronous using the DQS strobes.

DQ_B[63:0]

I/O

SSTL-2

Data: These signals are the 64-bit data bus, running at 2x data rate. The

data is source synchronous using the DQS_x strobes.

DQS_B[17:0]

I/O

SSTL-2

Data Strobes: These signals provide the timing information for the data and

ECC bits. They are driven by the source of the data; nine required for x8 and

x16 RAMs, eighteen required for x4 RAMs. Mapping to data and ECC

signals is shown in the functional description. When accessing x8 or x16

DRAM rows, DQS_B[17:9] are driven low during write cycles since these

pins will be connected to the DM (data mask) inputs of the DRAMs on the

DIMM.

CMDCLK_B[7:0]

CMOS

Differential Clock: These signals are outputs to the DIMMs. Commands

are referenced to the rising edge of CMDCLK_x and the falling edge of

CMDCLK_x#. One per DIMM for registered DIMMs, three per DIMM for

unbuffered DIMMs.

The mapping is shown in the table below:

• CK0/CK0# are at pins 137 and 138 of the DIMM.

• CK1/CK1# are at pins 16 and 17 of the DIMM.

• CMDCLK_B6 is multiplexed with CS_B5#

Signal 2 DIMM 3 DIMM

CMDCLK_B7 DIMM 1 CK2

CMDCLK_B6/CS_B5# DIMM 0 CK2

CMDCLK_B5 DIMM 1 CK1

CMDCLK_B4 DIMM 0 CK1

CMDCLK_B3

CMDCLK_B2 DIMM 2 CK0

CMDCLK_B1 DIMM 1 CK0 DIMM 1 CK0

CMDCLK_B0 DIMM 0 CK0 DIMM 0 CK0