Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 23
Signal Description
2.1 Host Interface Signals
Table 2-1. Host Interface Signals (Sheet 1 of 3)
Signal Name Type Description
ADS#
I/O
AGTL+
Address Strobe: The system bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
AP[1:0]#
I/O
AGTL+
Address Parity: The AP[1:0]# lines are driven by the request initiator and
provide parity protection for the Request Phase signals. AP[1:0]# are common
clock signals and are driven one common clock after the Request Phase.
Address parity is correct if there are an even number of electrically low signals
(low voltage) in the set consisting of the covered signals plus the parity signal.
Note that the MCH only connects to HA[35:3]#.
The MCH may be configured to send an error message to the Intel
®
ICH4 over
HI_A when it detects an error on one of the AP[1:0]# signals.
XERR#
I
AGTL+
Bus Error: This signal can be connected to the MCERR# signal or IERR#
signal, depending on system usage. The MCH detects an electrical high-to-low
transition on this input signal and sets the correct error bit. The MCH will take no
other action except setting that bit.
BINIT#
I
AGTL+
Bus Initialize: This signal indicates an unrecoverable error and can be driven
by the processor.It is latched by the MCH.
BNR#
I/O
AGTL+
Block Next Request: This signal is used to block the current request bus
owner from issuing a new requests. This signal is used to dynamically control
the system bus pipeline depth.
BPRI#
O
AGTL+
Priority Agent Bus Request: The MCH is the only Priority Agent on the
system bus. It asserts this signal to obtain the ownership of the address bus.
The MCH has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal is
asserted.
BREQ0#
I/O
AGTL+
Bus Request 0#: The MCH pulls the processor bus, BREQ0# signal low during
CPURST#. The signal is sampled by the processors on the active-to-inactive
transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The
minimum hold time is 2 HCLKs and the maximum hold time is 20 HCLKs.
BREQ0# should be Tristate after the hold time requirement has been satisfied.
CPURST#
O
AGTL+
CPU Reset: The CPURST# pin is an output from the MCH. The MCH asserts
CPURST# while RSTIN# (PCIRST# from ICH4) is asserted and for
approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the
processors to begin execution in a known state.
DBSY#
I/O
AGTL+
Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER#
O
AGTL+
Defer: This signal, when asserted, indicates that the MCH will terminate the
transaction currently being snooped with either a deferred response or with a
retry response.
DEP[3:0]#
I/O
AGTL+
Host Data Parity: The DEP[3:0]# signals provide parity protection for
HD[63:0]#. The DEP[3:0]# signals are common clock signals and are driven
one common clock after the data phases they cover. DEP[3:0]# are driven by
the same agent driving HD[63:0]#.
Data parity is correct if there are an even number of electrically low signals (low
voltage) in the set consisting of the covered signals plus the parity signal.
DINV[3:0]#
I/O
AGTL+
4x
Dynamic Bus Inversion: These signals are driven along with the HD[63:0]#
signals. They indicate when the associated signals are inverted. DINV[3:0]# are
asserted such that the number of data bits driven electrically low (low voltage)
within the corresponding 16 bit group never exceeds 8.