Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 161
Functional Description
5.4.5 AGP Target Operations
As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH
supports AGP target interface to main memory only. The MCH supports interleaved AGP and PCI
transactions.
5.4.6 Coherency
Coherency with the processor caches depends on the mode of operation and the cycle type. The
AGP Specification 2.0 requires only that PCI semantic transactions are coherent. The AGP
Specification 3.0 requires that AGP semantic asynchronous transactions outside of the aperture be
coherent as well as PCI semantic transactions. All other transactions are non-coherent in the MCH
to improve performance. Table 5-4 summarizes the transaction coherency.
Table 5-3. AGP 3.0 and AGP 2.0 Support Command Types
GC/BE[3:0]#
(GC#/BE[3:0])
Encoding
AGP 3.0 Command AGP 2.0 Command
0000 Read (Asynchronous) Read (Low Priority)
0001 Reserved Read (High Priority)
0010 Reserved Reserved
0011 Reserved Reserved
0100 Write (Asynchronous) Write (Low Priority)
0101 Reserved Write (High Priority)
0110 Reserved Reserved
0111 Reserved Reserved
1000 Reserved Long Read (Low Priority)
1001 Reserved Long Read (High Priority)
1010 Flush Flush (Low Priority)
1011 Reserved Reserved
1100 Fence (for reads & writes) Fence (Low Priority)
1101 Reserved (was DAC cycle) Reserved (was DAC cycle)
1110 Reserved Reserved
1111 Reserved Reserved
Table 5-4. AGP Summary of Transaction Coherency
Mode Async Access type Aperture Coherent Comments
AGP 8x Async AGP Inside No
AGP 8x Async AGP Outside Yes
AGP4x/2x/1x Hi/Lo Prio AGP Either No
All N/A PCI Either Yes