Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 141
Register Description
3.9.13 SERRCMD2—SERR Command Register (D2:F1)
Address Offset: A0h
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SERR will be generated when the associated flag is set in FERR
or NERR. When an error flag is set in the FERR or NERR Register, it can generate an SERR, SMI,
or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one
message type can be enabled.
Bits
Default,
Access
Description
7:6 Reserved
5
R/W
0b
SERR on MCH Master Abort to a HI_B Request Enable.
0 = No SERR generation
1 = Generate SERR if bit 5 is set in HIB_FERR or HIB_NERR
4
R/W
0b
SERR on Received Target Abort on HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in HIB_FERR or HIB_NERR
3
R/W
0b
SERR on Correctable Error on Header/Address from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 3 is set in HIB_FERR or HIB_NERR
2
R/W
0b
SERR on Correctable Error on Data from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 2 is set in HIB_FERR or HIB_NERR
1
R/W
0b
SERR on Uncorrectable Error on Header/Address from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 1is set in HIB_FERR or HIB_NERR
0
R/W
0b
SERR on Uncorrectable Error on Data Transfer from HI_B Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in HIB_FERR or HIB_NERR