Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 127
Register Description
3.8.8 MLT2—Master Latency Timer (Scratch Pad) Register
(D2:F0)
Address Offset: 0Dh
Default Value: 00h
Attribute: R/W, RO
Size: 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”
3.8.9 HDR2—Header Type Register (D2:F0)
Address Offset: 0Eh
Default Value: 01h or 81h
Attribute: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
3.8.10 PBUSN2—Primary Bus Number Register (D2:F0)
Address Offset: 18h
Default Value: 00h
Attribute: RO
Size: 8 bits
This register identifies that virtual PCI-to-PCI bridge is connected to bus #0.
Bits
Default,
Access
Description
7:3
00000b
R/W
Scratch pad MLT (NA7.3). These bits return the value with which they are written;
however, they have no internal function and are implemented as a scratch pad to avoid
confusing software.
2:0 Reserved
Bits
Default,
Access
Description
7:0
01h or
81h
RO
Header Type Register (HDR). This read only field indicates whether Device 2 is a
multi-function device.
01 = Single Function device (Function 1 is disabled in Device 0, offset E0h) with bridge
layout.
81 = Multi Function device (Function 1 is enabled in Device 0, offset E0h) with bridge
layout.
Bits
Default,
Access
Description
7:0
00h
RO
Primary Bus Number (BUSN). Hardwired to 00h. Configuration software typically
programs this field with the number of the bus on the primary side of the bridge. Since
device 2 is an internal device and its primary bus is always 0, these bits are read only as
00h.