Hub Datasheet

124 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.8.3 PCICMD2—PCI Command Register (D2:F0)
Address Offset: 04–05h
Default Value: 0000h
Attribute: RO, R/W
Size: 16 bits
Many of these bits are not applicable since the primary side of this device is not an actual PCI bus.
Bits
Default,
Access
Description
15:10 Reserved
9
0b
RO
Fast Back-to-Back Enable (FB2B). Hardwired to 0. Not Applicable.
8
0b
R/W
SERR Message Enable (SERRE). This bit is a global enable bit for Device 2 SERR
messaging. The MCH does not have an SERR# signal. The MCH communicates the
SERR# condition by sending an SERR message to the Intel
®
ICH4.
0 = Disable. SERR message is not generated by the MCH for Device 2.
1 = Enable. MCH is enabled to generate SERR messages over HI_A for specific
Device 2 error conditions.
7
0b
RO
Address/Data Stepping (ADSTEP). Hardwired to 0. Not applicable.
6
0b
RO
Parity Error Enable (PERRE). Hardwired to 0. Parity checking is not supported on the
primary side of this device.
5 Reserved
4
0b
RO
Memory Write and Invalidate Enable (MWIE). Hardwired to 0. Not applicable.
3
0b
RO
Special Cycle Enable (SCE). Hardwired to 0. Not applicable.
2
0b
R/W
Bus Master Enable (BME). This bit does not have a function. It is a Read/Write bit for
compatibility with compliance testing software.
1
0b
R/W
Memory Access Enable (MAE).
0 = Disable. All of device 2’s memory space is disabled.
1 = Enable. Enables the Memory and Pre-fetchable memory address ranges defined in
the MBASE2, MLIMIT2, PMBASE2, and PMLIMIT2 registers.
0
0b
R/W
IO Access Enable (IOAE).
0 = Disable. All of device 2’s I/O space is disabled.
1 = Enable. Enables the I/O address range defined in the IOBASE2 and IOLIMIT2
registers.