Specification Update
Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 53
Specification Update January 2015
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF141 Intel ® QuickData Technology DMA Engine Read Request that
Receives a Master Abort or Completer Abort Will Hang
Problem: If Intel ® QuickData Technology DMA receives a read completion with a Master Abort or
Completer Abort completion, it will cause a system hang.
Implication: Due to this erratum, the system may hang.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF142 PCIe* TLP Translation Request Errors Are Not Properly Logged For
Invalid Memory Writes
Problem: A PCIe Memory Write TLP (Transaction Layer Packet) with an AT field value of 01b
(address translation request) does not set the UR (Unsupported Request) bit
(UNCERRSTS CSR, Bus 0; Device 0; Function 0; Offset 0x14C; Bit 20) as required by
the PCIe Base Specification.
Implication: System or software monitoring error status bits may not be notified of an unsupported
request. When this erratum occurs, the processor sets the
'advisory_non_fatal_error_status' bit (CORERRSTS CSR, Bus 0; Device 0; Function 0;
Offset 0x158; Bit 13) and drops the failing transaction.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF143 Threshold-Based Status Indicator Not Updated After a UC or UCR
Occurs
Problem: In Machine Check Status MSRs for the cache, bits 54:53 are defined as the Threshold-
based Error Status Indicator for cache errors. If a UC (uncorrectable error) or UCR
(uncorrectable recoverable error) occurs in the cache, additional correctable errors that
occur in the cache that exceed the threshold value will not cause the Threshold-based
Error Status Indicator to change from Green to Yellow status once UC or UCR is
indicated.
Implication: After OS recovery of UCR errors without PCC (processor context corrupt), the
Threshold-based Error Status data may not have been updated for CE (correctable
errors) during the window of time from the UCR error until the software clears the
IA32_MCi_STATUS MSRs.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF144 PCIe* Slave Loopback May Transmit Incorrect Sync Headers
Problem: The PCIe Base Specification requires that, in the Loopback.Active state, a loopback
slave re-transmits the received bit stream bit-for-bit on the corresponding Tx. If the
link is directed to enter loopback slave mode at 8 GT/s via TS1 ordered sets with both
the Loopback and Compliance Receive bits set, the processor may place sync headers
in incorrect locations in the loopback bit stream.
Implication: In PCIe CEM (Card Electromechanical specification) Rx compliance testing directing the
link to loopback slave mode, the received data may not be correctly re-transmitted on
the Tx, causing the test to fail.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.