Guidelines

Packaging Technology
R
Intel
®
E7500 MCH Thermal and Mechanical Design Guidelines 11
2 Packaging Technology
The E7500 chipset consists of three individual components: E7500 MCH, 82870P2 P64H2, and
82801CA ICH3-S. The E7500 MCH utilizes a 42.5 mm, 6-layer FC-BGA package shown in
Figure 3 and Figure 2. For information on the P64H2 package, refer to the Intel
®
82870P2
PCI/PCI-X 64-bit Hub 2 (P64H2) Thermal and Mechanical Design Guidelines and the Intel
®
82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) Datasheet. For information on the ICH3-S package,
refer to the Intel
®
82801CA I/O Controller Hub 3 (ICH3-S) Datasheet.
Figure 2. Intel
®
E7500 MCH Package Dimensions (Side View)
1.10 ± 0.10 mm
Die
Substrate
0.60 ± 0.10 mm
Seating Plane
Package_Dimensions_Side
1.940 ± 0.150 mm
0.20 –C–
See note 3.
NOTES:
1. All dimensions are in millimeters.
2. Substrate thickness and package overall height are thicker than standard 492-L PBGA.
3. Primary datum –C– and seating plane are defined by the spherical crowns of the solder balls.
4. All dimensions and tolerances conform to ANSI Y14.5M–1982.