Specification Update

Intel
®
E7320 Memory Controller Hub (MCH) Specification Update 17
Errata
Workaround: Limit the uninterrupted duration (total data payload size) for transfers between peer PCI Express
ports, such that no one continuous transfer will exceed a duration of 16.7 ms. For reference, each
x4 PCI Express port is capable of transferring well over 12 MB of data in 16.7 ms, thus an
uninterrupted blockage of such duration is not expected to occur unless extreme circumstances are
contrived.
Status: For the steppings effected, see the Summary Table of Changes.
25. SMBDAT and SMBCLK signals pulled down in S5
Problem: According to SMBus Specification 2.0 the SMBDAT and SMBCLK signals are to float while in the
S5 state. Due to device protection circuitry these signals are pulled down while in the S5 state.
Implication: Devices on auxiliary power such as a BMC that share an SMBus connection with the MCH will not
be able to signal on the SMBus in the S5 state due to the signals being pulled down.
Workaround: A mux can be incorporated into the SMBus to disconnect the MCH when the platform goes into the
S5 state.
Status: For the steppings effected, see the Summary Table of Changes.
26. Multiple PCI Express protocol errors may result in fatal receiver overflow
Problem: If a PCI Express device connected to the MCH generates multiple transaction layer protocol errors,
including, unexpected completion packets or malformed transaction layer packets (TLPs) that
otherwise pass all link-layer error checking, and have the correct alignment on the interface, the
MCH may experience a fatal receiver overflow.
Implication: If the above conditions are met, The MCH may detect and log a “fatal” receiver overflow error.
MCH behavior in the presence of this error is consistent with the specification, in that continued
operation on the port after such an error may be unreliable.
Workaround: Intel recommends avoiding use of PCI Express devices that generate unexpected completion or
malformed TLP protocol violations. If this is unavoidable, the receiver overflow error detected by
the MCH may be escalated to a system event (e.g.: SERR#) that prevents continued operation on
the compromised link.
Status: For the steppings effected, see the Summary Table of Changes.
27. System marginalities may result in spurious link-down error events on
power state changes
Problem: On system power state changes (S3, S4, and S5) PCI Express devices are placed in the D3 device
power state by the operating system, which results in automatic negotiation with the MCH to enter
the L1 link state. In systems where the cumulative noise present at the MCH receiver pins exceeds
the MCH receiver threshold for detecting Electrical Idle, the transition into L1 may fail to complete
normally, ultimately resulting in a spurious link-down error from the MCH. If link down error (D2-
7:F0:R140h, bit 11) is escalated using a fatal system error (SERR#) mechanism, a blue-screen may
result on exposed systems.
The PCI Express specification for Electrical Idle at the receiver is 65 mV peak-peak differential,
and characterization of the MCH indicates that some lanes on some devices are marginal with
respect to this specification. While L1 failures should be exceedingly rare, Intel recognize that this
specification is difficult to meet, and acknowledge the exposure
Implication: Systems with sufficient noise at the MCH receivers and a BIOS profile that escalates the “link
down error” as a fatal system event may be exposed to blue-screen occurrence on system power
state transitions. Exposure to the error increases with the cumulative noise (platform noise + silicon
noise) present at the MCH receivers when the link is in Electrical Idle. Systems utilizing a BIOS
configuration that does not escalate the “link down error” as a fatal error are not exposed.