Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-71
INSTRUCTION FORMATS AND ENCODINGS
CVTSI2SD—Convert Doubleword
Integer to Scalar Double-Precision
Floating-Point Value
r32 to xmmreg1 1111 0010:0000 1111:0010 1010:11 xmmreg r32
mem to xmmreg 1111 0010:0000 1111:0010 1010: mod xmmreg r/m
CVTSD2SI—Convert Scalar Double-
Precision Floating-Point Value to
Doubleword Integer
xmmreg to r32 1111 0010:0000 1111:0010 1101:11 r32 xmmreg
mem to r32 1111 0010:0000 1111:0010 1101: mod r32 r/m
CVTTPD2PI—Convert with Truncation
Packed Double-Precision Floating-
Point Values to Packed Doubleword
Integers
xmmreg to mmreg 0110 0110:0000 1111:0010 1100:11 mmreg xmmreg
mem to mmreg 0110 0110:0000 1111:0010 1100: mod mmreg r/m
CVTTSD2SI—Convert with
Truncation Scalar Double-Precision
Floating-Point Value to Doubleword
Integer
xmmreg to r32 1111 0010:0000 1111:0010 1100:11 r32 xmmreg
mem to r32 1111 0010:0000 1111:0010 1100: mod r32 r/m
CVTPD2PS—Covert Packed Double-
Precision Floating-Point Values to
Packed Single-Precision Floating-
Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1010:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1010: mod xmmreg r/m
CVTPS2PD—Covert Packed Single-
Precision Floating-Point Values to
Packed Double-Precision Floating-
Point Values
xmmreg to xmmreg 0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1010: mod xmmreg r/m
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding