Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-69
INSTRUCTION FORMATS AND ENCODINGS
B.8 SSE2 INSTRUCTION FORMATS AND ENCODINGS
The SSE2 instructions use the ModR/M format and are preceded by the 0FH prefix
byte. In general, operations are not duplicated to provide two directions (that is,
separate load and store variants).
The following three tables show the formats and encodings for the SSE2 SIMD
floating-point, SIMD integer, and cacheability instructions, respectively. Some SSE2
instructions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte
opcode. These prefixes are included in the tables.
B.8.1 Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction
is operating on. When this field is used, it is located in bits 1 and 0 of the second
opcode byte. Table B-24 shows the encoding of this gg field.
Table B-24. Encoding of Granularity of Data Field (gg)
gg Granularity of Data
00 Packed Bytes
01 Packed Words
10 Packed Doublewords
11 Quadword
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions
Instruction and Format Encoding
ADDPD—Add Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1000:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1000: mod xmmreg r/m
ADDSD—Add Scalar Double-Precision
Floating-Point Values
xmmreg to xmmreg 1111 0010:0000 1111:0101 1000:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:0101 1000: mod xmmreg r/m
ANDNPD—Bitwise Logical AND NOT
of Packed Double-Precision Floating-
Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 0101:11 xmmreg1
xmmreg2