Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-62 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
mem to r32 1111 0011:0000 1111:0010 1100: mod r32 r/m
DIVPS—Divide Packed Single-Precision
Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1110: mod xmmreg r/m
DIVSS—Divide Scalar Single-Precision
Floating-Point Values
xmmreg to xmmreg 1111 0011:0000 1111:0101 1110:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 1110: mod xmmreg
r/m
LDMXCSR—Load MXCSR Register State
m32 to MXCSR 0000 1111:1010 1110:mod
A
010 mem
MAXPS—Return Maximum Packed
Single-Precision Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1111: mod xmmreg r/m
MAXSS—Return Maximum Scalar
Double-Precision Floating-Point Value
xmmreg to xmmreg 1111 0011:0000 1111:0101 1111:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 1111: mod xmmreg
r/m
MINPS—Return Minimum Packed
Double-Precision Floating-Point
Values
xmmreg to xmmreg 0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1101: mod xmmreg r/m
MINSS—Return Minimum Scalar Double-
Precision Floating-Point Value
xmmreg to xmmreg 1111 0011:0000 1111:0101 1101:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 1101: mod xmmreg
r/m
Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format Encoding