Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-17

INSTRUCTION FORMATS AND ENCODINGS

memory 1111 011w : mod 010 r/m

OR – Logical Inclusive OR

register1 to register2 0000 100w : 11 reg1 reg2

register2 to register1 0000 101w : 11 reg1 reg2

memory to register 0000 101w : mod reg r/m

immediate to register 1000 00sw : 11 001 reg : immediate data

immediate to AL, AX, or EAX 0000 110w : immediate data

immediate to memory 1000 00sw : mod 001 r/m : immediate data

OUT – Output to Port

fixed port 1110 011w : port number

variable port 1110 111w

OUTS – Output to DX Port 0110 111w

POP – Pop a Word from the Stack

memory 1000 1111 : mod 000 r/m

POP – Pop a Segment Register from the Stack

(Note: CS cannot be sreg2 in this usage.)

segment register DS, ES 000 sreg2 111

segment register SS 000 sreg2 111

segment register FS, GS 0000 1111: 10 sreg3 001

POPA/POPAD – Pop All General Registers 0110 0001

POPF/POPFD – Pop Stack into FLAGS or

EFLAGS Register

1001 1101

PUSH – Push Operand onto the Stack

memory 1111 1111 : mod 110 r/m

immediate 0110 10s0 : immediate data

Table B-13. General Purpose Instruction Formats and Encodings

for Non-64-Bit Modes (Contd.)

Instruction and Format Encoding