Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B A-9
OPCODE MAP
Table A-2. One-byte Opcode Map: (00H — F7H) *
01 2 3456 7
0 ADD PUSH
ES
i64
POP
ES
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
1 ADC PUSH
SS
i64
POP
SS
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
2 AND SEG=ES
(Prefix)
DAA
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
3 XOR SEG=SS
(Prefix)
AAA
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
4 INC
i64
general register / REX
o64
Prefixes
eAX
REX
eCX
REX.B
eDX
REX.X
eBX
REX.XB
eSP
REX.R
eBP
REX.RB
eSI
REX.RX
eDI
REX.RXB
5 PUSH
d64
general register
rAX/r8 rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15
6 PUSHA
i64
/
PUSHAD
i64
POPA
i64
/
POPAD
i64
BOUND
i64
Gv, Ma
ARPL
i64
Ew, Gw
MOVSXD
o64
Gv, Ev
SEG=FS
(Prefix)
SEG=GS
(Prefix)
Operand
Size
(Prefix)
Address
Size
(Prefix)
7 Jcc
f64
, Jb - Short-displacement jump on condition
O NO B/NAE/C NB/AE/NC Z/E NZ/NE BE/NA NBE/A
8
Immediate Grp 1
1A
TEST XCHG
Eb, Ib Ev, Iz Eb, Ib
i64
Ev, Ib Eb, Gb Ev, Gv Eb, Gb Ev, Gv
9NOP
PAUSE(F3)
XCHG r8, rAX
XCHG word, double-word or quad-word register with rAX
rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15
A MOV MOVS/B
Xb, Yb
MOVS/W/D/Q
Xv, Yv
CMPS/B
Xb, Yb
CMPS/W/D
Xv, Yv
AL, Ob rAX, Ov Ob, AL Ov, rAX
B MOV immediate byte into byte register
AL/R8L, Ib CL/R9L, Ib DL/R10L, Ib BL/R11L, Ib AH/R12L, Ib CH/R13L, Ib DH/R14L, Ib BH/R15L, Ib
C
Shift Grp 2
1A
RETN
f64
Iw
RETN
f64
LES
i64
Gz, Mp
LDS
i64
Gz, Mp
Grp 11
1A
- MOV
Eb, Ib Ev, Ib Eb, Ib Ev, Iz
D
Shift Grp 2
1A
AAM
i64
Ib
AAD
i64
Ib
XLAT/
XLATB
Eb, 1 Ev, 1 Eb, CL Ev, CL
E LOOPNE
f64
/
LOOPNZ
f64
Jb
LOOPE
f64
/
LOOPZ
f64
Jb
LOOP
f64
Jb
JrCXZ
f64
/
Jb
IN OUT
AL, Ib eAX, Ib Ib, AL Ib, eAX
FLOCK
(Prefix)
REPNE
(Prefix)
REP/
REPE
(Prefix)
HLT CMC
Unary Grp 3
1A
Eb Ev