Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-332 Vol. 2B

INSTRUCTION SET REFERENCE, N-Z

STI—Set Interrupt Flag

Description

If protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF)

in the EFLAGS register. After the IF flag is set, the processor begins responding to

external, maskable interrupts after the next instruction is executed. The delayed

effect of this instruction is provided to allow interrupts to be enabled just before

returning from a procedure (or subroutine). For instance, if an STI instruction is

followed by an RET instruction, the RET instruction is allowed to execute before

external interrupts are recognized

. If the STI instruction is followed by a CLI instruc-

tion (which clears the IF flag), the effect of the STI instruction is negated.

The IF flag and the STI and CLI instructions do not prohibit the generation of excep-

tions and NMI interrupts. NMI interrupts (and SMIs) may be blocked for one macro-

instruction following an STI.

When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than

3; STI sets the VIF flag in the EFLAGS register, leaving IF unaffected.

Table 4-4 indicates the action of the STI instruction depending on the processor’s

mode of operation and the CPL/IOPL settings of the running program or procedure.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Opcode Instruction

64-Bit

Mode

Compat/

Leg Mode Description

FB STI Valid Valid Set interrupt flag; external, maskable

interrupts enabled at the end of the

next instruction.

1. The STI instruction delays recognition of interrupts only if it is executed with EFLAGS.IF = 0. In a

sequence of STI instructions, only the first instruction in the sequence is guaranteed to delay

interrupts.

In the following instruction sequence, interrupts may be recognized before RET executes:

STI

RET