Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-241
INSTRUCTION SET REFERENCE, N-Z
RDPMC—Read Performance-Monitoring Counters
Description
Loads the 40-bit performance-monitoring counter specified in the ECX register into
registers EDX:EAX. The EDX register is loaded with the high-order 8 bits of the
counter and the EAX register is loaded with the low-order 32 bits. The counter to be
read is specified with an unsigned integer placed in the ECX register.
The indices used to specify performance counters are model-specific and may vary
by processor implementations. See Table 4-2 for valid indices for each processor
family.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 33 RDPMC Valid Valid Read performance-monitoring
counter specified by ECX into
EDX:EAX.
Table 4-2. Valid Performance Counter Index Range for RDPMC
Processor Family
CPUID Family/Model/
Other Signatures
Valid PMC
Index Range 40-bit Counters
P6 Family 06H 0, 1 0, 1
Pentium
®
4, Intel
®
Xeon
processors
Family 0FH; Model 00H,
01H, 02H
≥ 0 and ≤ 17 ≥ 0 and ≤ 17
Pentium 4, Intel Xeon
processors
(Family 0FH; Model
03H, 04H, 06H) and (L3
is absent)
≥ 0 and ≤ 17 ≥ 0 and ≤ 17
Pentium M processors Family 06H, Model 09H,
0DH
0, 1 0, 1
64-bit Intel Xeon processors
with L3
(Family 0FH; Model
03H, 04H) and (L3 is
present)
≥ 0 and ≤ 25 ≥ 0 and ≤ 17
Intel
®
Core™ Solo and Intel
Core Duo processors
Family 06H, Model 0EH 0, 1 0, 1
Intel
®
Core™2 Duo processor,
Intel Xeon processor 5100
Series - general-purpose PMC
Family 06H, Model 0FH 0, 1 0, 1
Intel Core 2 Duo processor,
Intel Xeon processor 5100
Series - fixed-function PMC
Family 06H, Model 0FH 8000_0000H,
8000_0001H
0, 1