Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-65
INSTRUCTION FORMATS AND ENCODINGS
RSQRTSS—Compute Reciprocals of
Square Roots of Scalar Single-Precision
Floating-Point Value
xmmreg to xmmreg 1111 0011:0000 1111:0101 0010:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 0010 mod xmmreg r/m
SHUFPS—Shuffle Packed Single-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 0000 1111:1100 0110:11 xmmreg1 xmmreg2:
imm8
mem to xmmreg, imm8 0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPS—Compute Square Roots of
Packed Single-Precision Floating-Point
Values
xmmreg to xmmreg 0000 1111:0101 0001:11 xmmreg1 xmmreg 2
mem to xmmreg 0000 1111:0101 0001 mod xmmreg r/m
SQRTSS—Compute Square Root of
Scalar Single-Precision Floating-Point
Value
xmmreg to xmmreg 1111 0011:0000 1111:0101 0001:11 xmmreg1
xmmreg 2
mem to xmmreg 1111 0011:0000 1111:0101 0001:mod xmmreg r/m
STMXCSR—Store MXCSR Register State
MXCSR to mem 0000 1111:1010 1110:mod
A
011 mem
SUBPS—Subtract Packed Single-
Precision Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1100:mod xmmreg r/m
SUBSS—Subtract Scalar Single-
Precision Floating-Point Values
xmmreg to xmmreg 1111 0011:0000 1111:0101 1100:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 1100:mod xmmreg r/m
Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format Encoding