Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-31
INSTRUCTION FORMATS AND ENCODINGS
Divide RDX:RAX by qwordregister 0100 100B 1111 0111 : 11 110 qwordreg
AL, AX, or EAX by memory 0100 00XB 1111 011w : mod 110 r/m
Divide RDX:RAX by memory64 0100 10XB 1111 0111 : mod 110 r/m
ENTER – Make Stack Frame for High Level
Procedure
1100 1000 : 16-bit displacement : 8-bit level
(L)
HLT – Halt 1111 0100
IDIV – Signed Divide
AL, AX, or EAX by register 0100 000B 1111 011w : 11 111 reg
RDX:RAX by qwordregister 0100 100B 1111 0111 : 11 111 qwordreg
AL, AX, or EAX by memory 0100 00XB 1111 011w : mod 111 r/m
RDX:RAX by memory64 0100 10XB 1111 0111 : mod 111 r/m
IMUL – Signed Multiply
AL, AX, or EAX with register 0100 000B 1111 011w : 11 101 reg
RDX:RAX <- RAX with qwordregister 0100 100B 1111 0111 : 11 101 qwordreg
AL, AX, or EAX with memory 0100 00XB 1111 011w : mod 101 r/m
RDX:RAX <- RAX with memory64 0100 10XB 1111 0111 : mod 101 r/m
register1 with register2 0000 1111 : 1010 1111 : 11 : reg1 reg2
qwordregister1 <- qwordregister1 with
qwordregister2
0100 1R0B 0000 1111 : 1010 1111 : 11 :
qwordreg1 qwordreg2
register with memory 0100 0RXB 0000 1111 : 1010 1111 : mod reg
r/m
qwordregister <- qwordregister
withmemory64
0100 1RXB 0000 1111 : 1010 1111 : mod
qwordreg r/m
register1 with immediate to register2 0100 0R0B 0110 10s1 : 11 reg1 reg2 : imm
qwordregister1 <- qwordregister2 with sign-
extended immediate8
0100 1R0B 0110 1011 : 11 qwordreg1
qwordreg2 : imm8
qwordregister1 <- qwordregister2 with
immediate32
0100 1R0B 0110 1001 : 11 qwordreg1
qwordreg2 : imm32
memory with immediate to register 0100 0RXB 0110 10s1 : mod reg r/m : imm
qwordregister <- memory64 with sign-
extended immediate8
0100 1RXB 0110 1011 : mod qwordreg r/m :
imm8
qwordregister <- memory64 with immediate32 0100 1RXB 0110 1001 : mod qwordreg r/m :
imm32
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding