Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-22 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

SUB – Integer Subtraction

register1 to register2 0010 100w : 11 reg1 reg2

register2 to register1 0010 101w : 11 reg1 reg2

memory to register 0010 101w : mod reg r/m

immediate to register 1000 00sw : 11 101 reg : immediate data

immediate to AL, AX, or EAX 0010 110w : immediate data

immediate to memory 1000 00sw : mod 101 r/m : immediate data

TEST – Logical Compare

register1 and register2 1000 010w : 11 reg1 reg2

memory and register 1000 010w : mod reg r/m

immediate and register 1111 011w : 11 000 reg : immediate data

immediate and AL, AX, or EAX 1010 100w : immediate data

immediate and memory 1111 011w : mod 000 r/m : immediate data

UD2 – Undefined instruction 0000 FFFF : 0000 1011

VERR – Verify a Segment for Reading

memory 0000 1111 : 0000 0000 : mod 100 r/m

VERW – Verify a Segment for Writing

memory 0000 1111 : 0000 0000 : mod 101 r/m

WAIT – Wait 1001 1011

WBINVD – Writeback and Invalidate Data Cache 0000 1111 : 0000 1001

WRMSR – Write to Model-Specific Register 0000 1111 : 0011 0000

XADD – Exchange and Add

register1, register2 0000 1111 : 1100 000w : 11 reg2 reg1

memory, reg 0000 1111 : 1100 000w : mod reg r/m

XCHG – Exchange Register/Memory with

register1 with register2 1000 011w : 11 reg1 reg2

Table B-13. General Purpose Instruction Formats and Encodings

for Non-64-Bit Modes (Contd.)

Instruction and Format Encoding