Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-1
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
This appendix provides machine instruction formats and encodings of IA-32 instruc-
tions. The first section describes the IA-32 architecture’s machine instruction format.
The remaining sections show the formats and encoding of general-purpose, MMX, P6
family, SSE/SSE2/SSE3, x87 FPU instructions, and VMX instructions. Those instruc-
tion formats also apply to Intel 64 architecture. Instruction formats used in 64-bit
mode are provided as supersets of the above.
B.1 MACHINE INSTRUCTION FORMAT
All Intel Architecture instructions are encoded using subsets of the general machine
instruction format shown in Figure B-1. Each instruction consists of:
• an opcode
• a register and/or address mode specifier consisting of the ModR/M byte and
sometimes the scale-index-base (SIB) byte (if required)
• a displacement and an immediate data field (if required)
The following sections discuss this format.
Figure B-1. General Machine Instruction Format
ModR/M Byte
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7-6 5-3 2-07-6 5-3 2-0
T T T T T T T T T T T T T T T T
Mod Reg* R/M
Scale Index Base
d32 | 16 | 8 | Noned32 | 16 | 8 | None
SIB Byte
Address Displacement
(4, 2, 1 Bytes or None)
Immediate Data
(4,2,1 Bytes or None)
Register and/or Address
Mode Specifier
Legacy Prefixes REX Prefixes
7 6 5 4 3 2 1 0
T T T T T T T T
(optional)
Grp 1, Grp 2,
Grp 3, Grp 4
(optional)
NOTE:
* The Reg Field may be used as an opcode
extension field (TTT) and as a way to encode
diagnostic registers (eee).
1, 2, or 3 Byte Opcodes (T = Opcode bit)