Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-304 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
SHUFPD—Shuffle Packed Double-Precision Floating-Point Values
Description
Moves either of the two packed double-precision floating-point values from destina-
tion operand (first operand) into the low quadword of the destination operand;
moves either of the two packed double-precision floating-point values from the
source operand into to the high quadword of the destination operand (see
Figure 4-13). The select operand (third operand) determines which values are
moved to the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. The select operand is an 8-bit immediate: bit 0
selects which value is moved from the destination operand to the result (where 0
selects the low quadword and 1 selects the high quadword) and bit 1 selects which
value is moved from the source operand to the result. Bits 2 through 7 of the select
operand are reserved and must be set to 0.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Opcode Instruction
64-
Bit
Mode
Compat/
Leg Mode Description
66 0F C6 /r
ib
SHUFPD xmm1,
xmm2/m128, imm8
Valid Valid Shuffle packed double-
precision floating-point values
selected by imm8 from xmm1
and xmm2/m128 to xmm1.
Figure 4-13. SHUFPD Shuffle Operation
X1 X0
Y1 Y0
Y1 or Y0
X1 or X0
SRC
DEST
DEST